Ceramic structures, usually and preferably multilayered, are used in the production of electronic substrates and devices. Multilayer ceramic substrates may comprise patterned metal layers which act as electrical conductors sandwiched between ceramic layers which act as insulators. The substrates may have termination pads for attachment to semiconductor chips, such as those for Controlled Collapse Chip Connection (C4), connector leads, capacitors, resistors, covers, or other device elements. C4 is also known as "solder bump" and "flip chip." Interconnection between conductive layers, which are separated by insulating layers, can be made through vias which are formed by filling holes in the insulating layers with a conductive metal paste.
Generally, ceramic layers are formed from ceramic green sheets which are prepared by mixing a ceramic particulate, a thermoplastic polymeric binder, plasticizers, and solvents. This mixture is spread or cast into ceramic sheets from which solvents are subsequently volatilized to provide coherent, self-supporting, flexible green sheets. After blanking, punching holes to act as vias, screening features with conductive/metallizing paste, stacking the green sheets, and laminating the green sheets to form a laminant, the green sheets are eventually fired at temperatures sufficient to drive off the polymeric binder resin and to sinter the ceramic particulates together into a densified ceramic substrate. Also, during the course of firing, the metallization paste features used to fill vias for interlayer connection and XY wiring are consolidated to form electrical conductors. The fired ceramic substrate also has surface metal features that provide electrical connection to the buried wiring within the substrate. These sheets may contain conducting (metal) lines. The sheets which are laminated together include holes within their surfaces to form the vias which allow electrical connections through the layer from the substrate to the chip.
The vias which are filled with a metal paste form metal columns perpendicular to the plane of the substrate once the components of these layers are fired to sinter the metal paste and ceramic into a monolithic. The result is a mechanically strong part with the desired electrical properties. After the monolithic is formed, the substrate may be attached to a semiconductor device such as the chip. C4 technology offers an advanced microelectronic chip packaging and connection technique over typical wire bond interconnection.
The basic idea of C4 is to connect chips, chip packages, or such other units by placing solder balls between two metallized surfaces of the units. These tiny balls of electrically conductive solder bridge the gaps between respective pairs of metal pads on the units being connected. Each pad to be connected has a corresponding pad on the surface of the other unit so that the pad arrangements are mirror images. As the units are aligned and exposed to temperatures above the melting point of the solder, the solder balls on the pads of the first unit become molten and join to corresponding conductive pads (having no solder balls) on the second unit, making permanent connections between respective pads.
A major application of C4 is in joining semiconductor devices (integrated circuits) to chip carriers. The C4 balls are typically placed on the chips while they are still in wafer form before dicing.
C4 allows a very high density of electrical interconnections. Unlike earlier techniques which made connections around the perimeter of a chip or a chip package, C4 allows one or more surfaces of a chip or package to be packed with pads. The maximum number of interconnections increases with the square of the chip size when using C4 arrays, while the maximum number of perimeter connections increases only linearly with the die size. Because the C4 balls can be made quite small, typically a few thousandths of an inch in diameter, the surface density of C4 connections can be on the order of thousands per square inch.
In general, the metal pastes used in fabricating multilayer ceramic (MLC) substrates for connection to C4 or other types of chips are comprised of metals with high melting points, such as molybdenum, tungsten, and gold. In addition, these pastes may use a metal which is less costly and has low electrical resistance, such as copper or its alloys. The paste also may include metal particles, an organic binder, solvents, plasticizers, and flow control agents.
Additives consisting of small amounts of powdered glass or ceramic particles (known as "frit") have been added to pastes in order to improve adhesiveness in certain non-C4 chip types. Normally, only about 5% or less frit, with about 10% being the highest amount usually added, is used in these compositions so that the highest possible electrical conductivity is maintained.
The paste will not shrink during sintering to the same extent or at the same rate as the ceramic component. When the respective shrinkages of the metal portion and ceramic portion are not "matched" appropriately, significant dimensional distortions can result in the fired ceramic/metal package. These can take the form of "via bulge," "camber," and other dimensional irregularities.
"Via bulge" is an out of flat condition of the top surfaces of the C4 vias. Large values of via bulge can make C4 or other types of chip attach difficult or impossible. "Camber," as referred to in this document, is any out-of-flat condition in the x-y plane. This may comprise a simple spherical or parabolic curvature, or a more convoluted configuration.
These defects on the surface of the substrate are undesirable because substantially "flat" substrates are required for practical substrate applications. Although the effects of these dimensional distortions are related to the overall sintering shrinkage of the several materials in the package, and ideally a perfect match might be expected to be desirable, in practice, a less-than-perfect match is frequently acceptable. Furthermore, the shrinkage in the package may, in fact, be an interactive process following a course different than expected from the shrinkage of the individual components fired separately or independently.
Unacceptable levels of via bulge or camber can prevent proper connection of device components and cause the device to be defective. In the case where camber is present, the substrate may be flattened by refiring. Other attempts to reduce the shrinkage difference of the metal and ceramic include controlling the metal particle size or introducing additives into the paste.
Nevertheless, these attempts at reducing mismatched shrinkage have been unsuccessful because via conductivity and bonding of the metal to the dielectric have suffered. In the case where via bulge is present, refiring may not be used, and the substrate may have to be rejected. Thus, these attempts at solving this problem have increased manufacturing cost, decreased yield, and caused other device defects.
The deficiencies of the conventional pastes show that a need still exists for a paste that will improve substrate dimensional control.